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Home > Products > Incisive functional verification > Design tasks > Transaction-based system verification
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Transaction-based system verification
The sheer size and complexity of system-level models coupled with the lengthy sequences generated by embedded software make traditional logic simulation alone insufficient for performing system-level verification. Engineers are turning to higher levels of abstraction with SystemC® transaction-level models (TLMs) and hardware-based acceleration/emulation as essential techniques for system-level verification.
The Incisive Enterprise family offers a comprehensive, transaction-based system verification solution that spans the entire verification process, from architectural validation to RTL simulation and full-system acceleration/emulation.
Plan-based verification with total coverage metrics
Cadence® is the first to offer a plan-based solution that automates regression runs, failure analysis, and coverage aggregation for both transaction-based system verification (TBSV) and signal-level tests across the entire flow. Incisive Enterprise Manager supports a total system coverage approach that combines directed test coverage from TBSV, software use cases and emulation, constrained random test coverage, and assertion coverage to provide an overall measure of progress toward closure. Assertion coverage is supported throughout the flow including SystemC TLMs, RTL simulation, formal analysis, acceleration, and emulation.
Mixed-language simulation with 100% IEEE-compliant SystemC language
The Incisive® Enterprise Simulator seamlessly combines SystemC TLMs with Verilog®, VHDL, SystemVerilog, and e models. The native SystemC compiler supports the entire IEEE 1666, OSCI® SystemC, SCV, and TLM standards. Built from a unified mixed-language kernel, it supports fully congruent transaction-based acceleration with the Palladium® series of accelerator/emulators.
Transaction-based acceleration
Both the Incisive Palladium and Xtreme® series of accelerator/emulators support transaction-based acceleration (TBA). The same SystemC TLMs used for system-level design and as reference models for RTL development can be used in conjunction with RTL acceleration. This environment increases performance substantially over simulation and signal-based hardware acceleration. Central to TBA's effectiveness is the Cadence unique congruency feature, which ensures the same results in simulation and acceleration without needing to change any design or testbench models.
Hybrid-mode
Hybrid mode combines transaction-based acceleration with in-circuit emulation in a single run. This capability enables verification scenarios with multiple concurrent sources of stimuli, originating from both software testbenches and physical target systems. This helps migrate the verification process smoothly from simulation to silicon, while optimizing performance.
Common debug environment
The Incisive SimVision common debug environment makes it easy to debug across multiple abstraction levels and language domains, allowing you to trace and capture transactions, signals, and unified assertions in a single window, even when using multiple engines. SimVision offers a comprehensive set of transaction-oriented recording, visualization, and analysis including the ability to measure bus-bandwidth utilization, peripheral usage, processor memory accesses, and functional coverage. This unified environment improves engineering productivity and streamlines communication between architects, hardware designers, verification specialists, and software developers.
Verification IP portfolio for transaction-based system verification (TBSV)
Cadence offers robust Verification IP (VIP) supporting the TBSV methodology. There are three classes of VIP available:
 | Transaction-based VIP: provides pre-built transactors for popular bus interfaces including AHB, AXI, PCI Express, and Ethernet. These models can be simulated or accelerated, while providing full congruency and reusability between engines. | | Assertion-based VIP: provides pre-built assertion protocol monitors including AHB, AXI, USB, and Ethernet. These models are available for simulation, acceleration, and emulation. | | SpeedBridge® rate adapters: provide in-circuit emulation and hybrid-mode transaction-based acceleration for fast HW/SW co-verification in conjunction with a target system. SpeedBridge adapters are available for PCI, PCI-X, PCI Express, USB, ARM®, video, audio, Ethernet protocols, and both SAS and SATA bus interfaces. |
Plan-to-Closure Methodology
The Incisive Plan to Closure Methodology and online knowledge system help guide teams through the TBSV process. It explains in detail how to incorporate TLMs into the simulation environment and how to reuse the same SystemC/RTL mixed environment and verification IP in simulation and acceleration using TBA .
The Incisive transaction-based system verification solution contains the following products and methodologies:
Resources
Webinar: Leveraging Transaction-Based System Verification to Increase Productivity Predictability and Quality
Techtorial: System-level Verification Process Automation Focus Event
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