Cadence functional Verification Kit for ARM

Jointly developed by Cadence and ARM, the Cadence® Functional Verification Kit for ARM offers a comprehensive verification solution specifically for engineers developing ARM® processor-based designs. The Kit contains ARM processor-based verification methodology and flows, a reference design platform, verification process automation (VPA) technology, and reusable verification IP. The proven Incisive® Plan-to-Closure Methodology from Cadence has been tailored specifically to ARM processor-based designs.

Combined with the Incisive functional verification platform and verification IP, the Kit addresses the verification of both hardware and software from block to chip to system levels. The Kit guides engineers through the following processes and flows to provide a streamlined path from verification plan to closure:

	Advanced verification architecture, maximizing reuse from block to chip to system
	Automated verification planning and management
	Architectural modeling for early HW/SW co-verification
	Assertion-based verification for formal analysis, simulation, acceleration, and emulation
	Testbench automation to address challenging corner-case bugs
	Certified ARM AMBA® verification IP and protocol compliance
	Transaction-based acceleration for high-performance RTL verification
	In-circuit emulation for system and software validation

Key benefits

	Increases predictability by automating the management of the verification process
	Ensures process management and AMBA specification compliance via an executable verification plan
	Reduces risk by leveraging an industry-proven plan-to-closure verification methodology
	Enables verification IP reuse across block, chip, and system levels
	Ensures product quality by verifying both HW and SW simultaneously at the block, chip, and system levels
	Improves productivity with easy-to-adopt architectural modeling techniques, formal analysis, simulation, advanced testbench, acceleration, emulation, and HW/SW co-verification
	Based on IEEE standard languages: e, SystemVerilog, SystemC®

Cadence Functional Verification Kit for ARM






	Cadence SoC Functional Verification Kit This new Kit offers design and verification teams a comprehensive solution to ease the adoption of new verification technologies and methodologies. New! SoC Functional Verification Kit Demo This demo highlights the SoC Functional Verification Kit and how functional verification methodologies go beyond basic tools.



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