Cadence RF SiP Methodology Kit


		Cadence Low-Power Methodology Kit


		Cadence RF SiP Methodology Kit


		Cadence AMS Methodology Kit


		Cadence RF Design Methodology Kit

Cadence RF SiP Methodology Kit

The Cadence® RF SiP Methodology Kit accelerates the application of advanced EDA technologies to system-in-package (SiP) designs for Radio Frequency (RF)/wireless applications. It provides methodologies that maximize design productivity and predictability for customers leveraging the advantages of SiP implementation. An integrated set of SiP design products built around proven methodologies—demonstrated on a segment representative design—enables complete front-to-back SiP design and implementation.

By combining comprehensive links between system design, physical implementation and manufacturing, the kit allows full-SiP electrical analysis and characterization of critical paths as well as behavioral modeling from overall system-level simulation through bottom-up verification.

Key benefits

	Combines system design, physical implementation and manufacturing in a complete, true IC/package co-design solution
	Provides a seamless flow starting at full-SiP electrical simulation, through a single schematic-driven layout implementation and ends with comprehensive signal integrity checks
	Achieves functional, performance, and closed-loop verification across multiple technologies and design domains including system-level, digital, mixed-signal, and analog/RF
	Improves simulation accuracy and completeness by effectively combining signal integrity analysis at SiP and parasitic extraction at IC-level
	Optimizes on and off chip configurations by managing inductor synthesis and passive component modeling

Cadence SiP design solution

Kit Contents

	A segment representative design—an 802.11 b/g WLAN RF SiP design that includes a Helic-based RF transceiver and analog baseband die in a 180 nm generic CMOS process
	AMS interface die in a 90 nm generic CMOS process
	Embedded and discrete passive off-chip components in a generic LTCC substrate
	Re-usable, pre-setup components from testbenches, models, and simulation plans for block and full-SiP level and physical implementation approaches
	Step-by-step examples on how to apply Cadence technologies to best achieve design success
	5-day applicability consulting








	Cadence SoC Functional Verification Kit This new Kit offers design and verification teams a comprehensive solution to ease the adoption of new verification technologies and methodologies. New! SoC Functional Verification Kit Demo This demo highlights the SoC Functional Verification Kit and how functional verification methodologies go beyond basic tools.



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Cadence Design Systems, Inc.