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 | Virtuoso Custom Design Platform L
Provides an entry-level configuration of the industry's leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design. |
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| Virtuoso Custom Design Platform XL
Extends the L family to provide higher levels of design assistance to the end-user, including 5x speed-up of common design tasks, constraint- and schematic-driven physical implementation, and other enhancements. |
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| Virtuoso Custom Design Platform GXL
Comprises the platform's most advanced configuration of design and analysis technologies, including expanded physical design capabilities and an enhanced simulation environment. |
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| Assura Design Rule Checker
Supports both interactive and batch operation modes and utilizes hierarchical processing to identify and correct design rule errors |
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| Assura Layout vs. Schematic
Ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout. Extracts devices and nets formed across layout hierarchy and compares them to the schematic netlist |
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| Assura Parasitic Extraction
Provides parasitic extraction on full-chip layouts with silicon accuracy |
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| Cadence Chip Optimizer
Cadence® Chip Optimizer is silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance. It addresses today's requirements for shorter time to convergence and time to volume. Cadence Chip Optimizer works seamlessly with the Cadence Encounter® digital IC design platform and the Virtuoso® custom design platform.
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| Cadence QRC Extraction
The industry's premier 3D full-chip parasitic extractor for fast and accurate implementation and validation of complex designs
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| Cadence Space-based Router
A silicon-proven, 3-D, hierarchical, grid-less, space-based, full-chip and block routing convergence system for advanced mixed-signal, analog, and custom digital designs at 65nm and below.
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| Virtuoso AMS Designer Simulator
Addresses mixed-signal simulation for the design and verification of mixed-signal SoCs |
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| Virtuoso Analog ElectronStorm Option
An option to the Virtuoso Analog Design Environment. Addresses electromigration validation for analog designs |
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| Virtuoso Analog Option
An option to the Virtuoso Analog Design Environment. Extends the VoltageStorm family of power integrity products to analog designs |
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| Virtuoso Passive Component Designer
Comprises a complete solution for the design, verification and modeling of spiral inductors, transformers and transmission lines. |
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| Virtuoso Chip Editor
Provides editing for full-chip finishing tasks and the. Fully interoperable with Encounter™ digital IC design platform and leverages the Virtuoso Layout Editor environment and infrastructure |
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| Virtuoso Digital Implementation
The Cadence Virtuoso Digital Implementation is a complete synthesis and place-and-route system for small digital block implementation in context of analog-driven, mixed-signal design methodology |
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| Virtuoso Layout Migrate
The physical layout migration tool that supports fast process and design rule migration of hard IP, custom digital designs, mixed-signal blocks, memories, and standard cell libraries |
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| Virtuoso Multi-mode Simulation
Combines four simulation engines to address analog, mixed-signal, RF, and full-chip design verification. Delivers SPICE, FastSPICE, RF, and analog mixed-signal capabilities for simulating analog, mixed-signal, or RF designs |
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| Virtuoso RET Suite
A powerful and comprehensive combination of design tools that brings full lithography awareness into the Virtuoso custom design platform. It embeds lithography expertise within the design environment, allowing a designer to create manufacturable designs. |
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| Virtuoso RF Designer
Virtuoso RF Designer is a comprehensive EM simulation and verification solution that is tightly integrated into the Virtuoso custom design platform. |
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| Virtuoso Schematic Editor
The designing composition environment that helps implement each stage of the design, from architectural definition using industry-standard language representations to final structural implementations done graphically |
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| Virtuoso Spectre Circuit Simulator
Provides simulations for analog and mixed-signal circuits and detailed transistor-level analysis in multiple domains |
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| Virtuoso Spectre RF Simulation Option
Provides simulations for RF and high-frequency ICs. Works with Virtuoso® Analog Design Environment to analyze RF and high-frequency designs |
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| Virtuoso UltraSim Full-chip Simulator
A Cadence FastSPICE simulator that verifies designs or systems |
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| Virtuoso XL Layout Editor
A high-end custom block authoring physical layout tool. Supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels |
