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 | Physical Verification System
System accelerates design signoff by orders
of magnitude compared to conventional tools. It facilitates multiple design turns per day for large 90nm and 65nm designs. Performance scales linearly and is limited only by the compute resources available.
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| Assura Design Rule Checker
Supports both interactive and batch operation modes and utilizes hierarchical processing to identify and correct design rule errors
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| Assura Layout vs. Schematic
Ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout. Extracts devices and nets formed across layout hierarchy and compares them to the schematic netlist |
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| Cadence CMP Predictor
Turns the uncertainty of process variation into predictable impacts, and then minimizes and accounts for these impacts throughout the design process.
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| Cadence Litho Electrical Analyzer
Cadence® Litho Electrical Analyzer is the industry's first complete
and silicon-correlated electrical DFM analysis product to help designers
using sub-90nm processes optimize and control the impact of lithography,
mask, etch, RET, OPC, and CMP effects on their chip parameters.
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| Cadence Litho Physical Analyzer
As the industry's most comprehesive foundry-certified model-based design
manufacturability checker, Cadence® Litho Physical Analyzer detects
manufacturability issues missed by traditional DRC check in a fraction
of the time required by solutions based on OPC and lithography simulation.
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| Cadence MaskCompose Suite
The MaskCompose Reticle and Wafer Synthesis Suite comprises a series
of software modules that speed production and reduce errors in the
tapeout flow.
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| Cadence QuickView Viewer
Cadence QuickView Layout and Manufacturing Data Viewer is an easy-to-use,
high-performance system for viewing and superimposing data in various formats.
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| Cadence QRC Extraction
The industry's premier 3D full-chip parasitic extractor for fast and accurate implementation and validation of complex designs
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| Diva Physical Verification
Provides real-time physical verification of cells, blocks, and small IC designs |
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| Dracula
Verification technology that provides a complete set of tools suitable for small cells up to very large ICs |
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| Encounter Test
Supports a unified test methodology from design to manufacturing, which helps design and test engineers reduce test cost, and offers superior test coverage which improves product quality
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