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 | First Encounter silicon virtual prototyping
First Encounter technology spans silicon virtual prototyping, automatic floorplanning, complete power-grid realization, hierarchical controls for partitioning and budgeting, and hierarchical clock-tree synthesis. |
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| SoC Encounter RTL-to-GDSII system
The SoC Encounter system furnishes an integrated RTL-to-GDSII system for advanced hierarchical designs up to 100M gates. It offers clock mesh synthesis, design for yield and mixed-signal capabilities, dataflow-driven macro placement, and nanometer routing. |
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| Encounter Timing System
Encounter Timing System offers a consistent, integrated static timing analysis (STA) environment for place-and-route optimization and signoff verification.
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| Encounter Library Characterizer
Encounter Library Characterizer is a complete characterization solution that delivers cutting-edge library models with precision, speed, and a simplified user interface.
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| Encounter RTL Compiler synthesis
Encounter RTL Compiler delivers production-proven global synthesis for faster, smaller, and low-power chips in less time. |
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| Encounter Conformal Equivalence Checker
Encounter Conformal Equivalence Checker can handle complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. It also performs functional checks to verify clock synchronization.
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| Encounter Conformal Constraint Designer
Encounter Conformal Constraint Designer automates the generation, validation, and refinement of constraints to ensure that SDC constraints and timing exceptions are valid throughout the entire design process, helping designers to reduce iterations and accelerate timing closure.
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| Encounter Conformal Low Power
Encounter Conformal Low Power helps designers verify and debug power-optimized multimillion-gate designs. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use.
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| Encounter Conformal ECO Designer
Encounter Conformal ECO Designer enables designers to implement RTL engineering
change orders (ECOs) for pre- and post-mask layout. It combines automatic ECO
analysis and design netlist modification with world-class equivalence checking
to provide superior performance, productivity, capacity, and ease-of-use. |
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| Encounter Test
Encounter Test delivers the industry's most advanced test solution from RTL to silicon. It helps you reduce cost-of-test and accelerate yield ramp with enhanced on-chip data compression and physically aware diagnostics capabilities.
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| CeltIC NDC
CeltIC Nanometer Delay Calculator (NDC) is an SI-aware delay calculator that provides you with a unified timing solution that accurately accounts for the impact of crosstalk and IR drop on both delay and functionality. |
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| Cadence Chip Optimizer
Cadence Chip Optimizer is silicon-proven, full-chip physical design optimization system that improves manufacturability, yield, and performance. It addresses today's requirements for shorter time to convergence and time to volume. Cadence Chip Optimizer works seamlessly with the Cadence Encounter digital IC design platform and the Virtuoso custom design platform.
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| Cadence QRC Extraction
The industry's premier 3D full-chip parasitic extractor for fast and accurate implementation and validation of complex designs
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| NanoRoute Ultra router
NanoRoute is a separate routing, optimization, verification, and chip-finishing technology that also is at the core of the Cadence SoC Encounter RTL-to-GDSII system |
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| VoltageStorm power analysis
VoltageStorm power-grid verification is the leading power-grid verification solution, and the first transistor-accurate power-grid analysis product fast enough for use during physical design. |
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| Fire & Ice QXC
Fire & Ice QXC has redefined the accuracy requirements for cell-based digital designs — it is 2X more accurate as other extraction technologies and handles in-die process variations that often occur in advanced processes as 130nm and below |
