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 | Incisive Manager
Incisive Mangement is an automated management system that guides the verification process and analyzes verification data, from planning to closure
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| Incisive Formal Verifier
Formal analysis used prior to testbench development and exposes corner-case bugs that are difficult or even impossible to find using simulation, acceleration, or emulation |
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| Incisive Specman Elite
Simplifies and speeds verification by automating test generation, capturing functional coverage, and enabling both code and behavioral re-use throughout the design cycle
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| Incisive AMS
Single-engine, analog/mixed-signal simulator that facilitates verification of the entire design, from conceptualization to physical realization |
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| Incisive HDL Simulator
Supports RTL simulation for both Verilog and VHDL. Its SystemVerilog support includes the design constructs routinely used by design engineers. Also offers integrated code coverage and SimVision graphical debug environment.
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| Incisive Design Team Simulator
Builds upon the HDL Simulator's capabilities, adding SystemVerilog testbench constructs SystemC, PSL, SVA, and OVL. HDL analysis, assertions, and functional coverage are included and SimVision is extended to support transactional analysis and debug.
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| Incisive Enterprise Simulator
Top of the line simulator in the Incisive platform supporting all languages and functionalities with the addition of the e language through tight integration with Specman Elite. It's the only simulator on the market that supports all languages and design abstractions, from the gate level all the way up to system-level modeling and verification.
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| Incisive Xtreme series
Provide simulation, acceleration and emulation that improves design team productivity and automates the verification process, from executable plan to closure.
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| Incisive Palladium series
Acceleration and emulation that delivers up to 100x for simulation acceleration and 10,000x for in-circuit emulation with multi-user capability and optional acceleration-on-demand |
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| Incisive Plan-to-Closure Methodology
Incisive Plan-to-Closure Methodology is a system of best known principles, practices, and procedures that automate and reduces risk in the verification of full-chips and SoCs |
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| Incisive XLD
Includes 10 licenses of an Incisive simulator with an acceleration-on-demand licensing option that allows you to swap nine licenses for additional accelerator/emulator capacity at runtime. |
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| Incisive Unified Simulator
Built on a single-kernel architecture, supports open design and verification standards and provides full transaction-level support, HDL analysis, unified test generation, simulation, and more. |
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| NC-SC
Runs transaction-level models 100x faster than RTL, supports SystemC® verification, and is ideal for architecture analysis, testbench development, and embedded SW verification |
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| NC-Verilog
Premier Verilog® simulator - delivers the highest performance and capacity with transaction/signal viewing and integrated coverage analysis |
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| NC-VHDL
Premier Verilog® simulator - delivers the highest performance and capacity with transaction/signal viewing and integrated coverage analysis |
