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High-speed PCB Design and Analysis
The Cadence® Allegro® system interconnect design platform enables collaborative design of high-performance interconnect across IC, package, and PCB domains. The platform's constraint-driven flow and co-design methodology optimizes system interconnect between I/O buffers and across ICs, packages, and PCBs, eliminating hardware re-spins, reducing costs and design cycles, and accelerating time to market.
Whether you are designing PCB systems with large number of high-speed nets or a system with small number that operate in Multi-gigahertz (MGH) range, Allegro PCB SI offers a scalable, complete and integrated solution for SI engineers and hardware engineers to explore and resolve electrical performance-related issues at every stage of the high-speed PCB system design cycle.
Allegro PCB Design XL series provides a complete, integrated design environment to shorten the design cycle of complex, dense digital systems containing a growing number of constrained nets. Increasing numbers of nets that operate with increasing edge rates and the need for higher throughput introduce new high-speed design challenges, such as timing analysis, crosstalk, and power delivery. The challenges must be addressed simultaneously and throughout the design cycle. High-speed designs with increasing number of constrained nets require users to follow a new methodology-one that ensures designs are completed in a shorter period of time while optimizing the chance of first pass success.
The need to provide ultra high bandwidth for data transfer coupled with pressures to get products to market faster has added many challenges for system designers. While technological advances—such as differential signals with embedded clocks (serial links), drivers with pre-emphasis, and receivers with equalization—allow engineers to architect systems that have higher performance and throughput, the tools to design such systems have not kept pace. This situation has forced engineers to use disparate standalone tools to design systems with high-speed signals, particularly those that operate in MGH range.
For differential signals used in serial link designs, system designers must ensure that timing and voltage margins are met (also known as achieving "acceptable eye opening"). Traditional circuit simulators are limited to about 1024 bits of custom stimulus pattern
length. This means that the effect of Inter Symbol Interference (ISI) is not adequately modeled by traditional
simulation solutions. To accurately predict the eye opening, you need tools that can simulate stimulus
patterns of over 1 million bits.
Signals operating in MGH range require a new generation of design tools to
manage challenges introduced in the design process. You need a set of tools that model each element of the signal's path quickly and accurately. At high frequencies, the losses on a signal mount as the signal travels through different discontinuities such as vias, connectors and different layers in one or more printed circuit boards. At Gigahertz frequencies, the loss in a transmission line can approximately be 0.25+ dB/inch, creating challenges for longer interconnects on PCB systems. Ensuring that losses in critical signals are acceptable is an important step in the design of MGH signals. To accomplish this, you need a way to do loss budget trade-offs using S-Parameters quickly and iteratively. You also need a way to change the MGH signals topology and within seconds be able to view the expected loss through the system interconnect.
Engineers need a way to perform loss budget trade-offs using S-Parameters, while achieving faster simulation of complex devices. MGH design further requires technology for simulating tens of thousands of bits quickly, and determining optimal configuration ("tap settings") of complex drivers/receivers. Engineers need a system that addresses their major design challenges in an integrated environment that is simple to use, and has productivity capabilities built in. Allegro PCB SI GXL offers engineers an easy-to-use and highly integrated virtual prototyping environment to meet today's MGH design challenges.
Allegro PCB SI and Allegro Design Entry HDL enable design engineers to develop optimum constraints through simulation early in the design cycle, enabling a constraint-driven high-speed PCB design flow. Allegro PCB Design XL series consumes these constraints to ensure the design is implemented correctly and optimizes the chance of first pass success. To manage the increasing number of constraints, Allegro Constraint Manager makes this collective process possible by providing a unified spreadsheet interface for capturing, managing, and verifying electrical constraints across the entire design flow.
To shorten the time it takes to design-in new complex devices with high-speed I/Os, Cadence has pioneered the concept of silicon design-in IP portfolios. Silicon design-in IP portfolios that have been distributed in the past can be found on Allegro SI community site.
Learn more about the benefits of silicon design-in IP portfolios in speeding implementation of complex new IC devices with high-speed I/Os.
| 600 series products and options |
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Allegro PCB SI
Complete high-speed design and analysis environment for high-speed digital systems
Allegro Design Entry HDL SI
High-speed design and analysis environment for hardware engineers to develop and specify constraints during logic design phase.
Allegro PCB Design XL series
High-speed design suite integrated with Constraint Manager.
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