Silicon Design-In
Time to volume production for IC manufacturers depends on quick adoption of new devices by systems companies. However, the combination of differing design environments, complex I/O structures, and multigigabit-speed data rates make new device simulation and implementation into a PCB system a complex and expensive process.
Innovative silicon design-in IP portfolios from Cadence and key industry partners tackle these issues. Using technology available in the Allegro PCB SI design and analysis environment, IC manufacturers can help shorten their customers' design-in time on complex silicon devices by providing an executable version of their design guides in the form of high-speed silicon design-in IP portfolios. These silicon design-in IP portfolios allow engineers to accurately simulate PCB topologies with minimal setup, enabling them to obtain accurate simulation results 20 times faster than would have been possible without silicon design-in IP.
Cadence silicon design-in IP portfolios include the following:
Memory interfaces
