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Home > Products > Allegro IC-PKG-PCB co-design > New 15.5 release highlights
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NEW 15.7 RELEASE HIGHLIGHTS
The 15.7 Cadence® Allegro® system interconnect design platform offers a range of products scaled to different printed circuit board (PCB) design complexities and also includes new products, Allegro Design Workbench XL and Allegro Design Publisher XL. This new release of the Allegro platform offers a tiered range of products to PCB designers, providing customers with multiple levels of technology tailored to specific levels of design complexity.
The new Allegro offerings comprise three levels: L, XL and GXL. The Allegro L product series provides PCB design products aimed at solving mainstream design challenges. The Allegro XL product series provides advanced PCB design products that address more complex and high-end design challenges through integrated constraint-driven automation and distributed team-based design productivity. The Allegro GXL product series provides differentiated PCB design products targeting leading-edge design challenges such as advanced package co-design and multi-GHz signal-integrity (SI) analysis.
With this latest release, a new board-level bus-analysis capability has been added to Allegro PCB SI, shortening time to verify source-synchronous signals used in interfaces such as DDR2 memories. Other enhancements associated with source-synchronous interfaces include support for On-Die Termination (ODT), association of clock, strobe signals to the bus, association of board-level custom stimulus and reports for setup and hold times. In addition, Allegro PCB Editor has been enhanced to shorten the time required to identify critical nets that will potentially have a return path problem.
Previous releases
The 15.5 Cadence® Allegro® system interconnect design platform enables team-based PCB design throughout the design flow to shorten design time and strengthen the IC design chain. This release provides enhancements from design entry to PCB design with new technology for real-time design partitioning, Design for Assembly (DFA), and an improved constraint-driven design flow.
Allegro 15.5 includes Allegro Design Editor 620, the industry's first multi-style design creation environment that helps speed design creation by up to 10 times. It also includes design partitioning technology that allows multiple PCB designers working concurrently on a layout to share access to a common database. With Allegro 15.5, the entire breadth of the Allegro product line has been enhanced with greater productivity and ease-of-use capabilities.
Allegro 15.5 is supported on the following platforms: Linux (Red Hat 7.3, 8.0, RHEL 3.0), Windows (2000 with Service Pack 4, XP Professional), Sun (Solaris 8, 9), HP (HP-UX 11.00, 11.11i), and IBM (AIX 5.1).
The 15.2 Cadence® Allegro® system interconnect design platform optimizes and accelerates high-performance, high-density interconnect design. The Allegro platform delivers proven, best-of-breed design and analysis tools to support a new generation co-design methodology that promotes collaboration across the entire system design chain. Electronics manufacturers will benefit from the Allegro platform's ability to minimize design iterations within and between the design domains of IC, package, and PCB design. The new platform provides a common constraint-driven flow across design entry, signal and power integrity, and comprehensively addresses the implementation of system interconnects. Illustrating this new co-design methodology, Cadence is introducing a new approach to silicon design-in kits with its PCI Express design chain.
Several new products are available in this release, including Allegro PCB SI 630, the PCB industry's most advanced solution for multi-gigahertz (MGH) design, Allegro Package Designer 620 and Allegro Package SI 620 for constraint-driven layout for the physical design of complex, high-density IC packages and addresses the needs of the engineer responsible for package-level tradeoff, characterization, analysis, and model extraction.
15.2 is supported on the following platforms: Linux (Red Hat 7.3, 8.0, 9.0, RHEL 3.0), Windows (2000 with Service Pack 3, XP Professional), Sun (Solaris 8, 9), HP (HP-UX 11.00, 11.11i), and IBM (AIX 5.1).
From high-speed, team-based PCB design environments and silicon-package-board co-design to the latest in personal productivity, Cadence offers an extensive range of industry-standard PCB solutions to accommodate your specific needs.
The new 15.1 PCB and IC Packaging design solutions release is available on Linux.
The 15.1 release addresses the growing complexity and speed of today's leading-edge PCB designs. Enhanced to address the monumental challenges of integrating nanometer-scale ICs into packages, onto boards, and into systems, the release includes new capabilities that allow engineers to effectively design and analyze the high-speed system interconnect. Advances in packaging technology automate and improve the design of stacked-die packages to support the growing system-in-package market. Productivity enhancements across the flow help customers get products into volume production faster.
15.1 is supported on the following platforms: Red Hat Linux 7.3, 8.0, Windows (2000 with Service Pack 2, and XP Professional), Sun (Solaris 7, 8, 9), HP (HP-UX 11.00 and 11.11i), and IBM (AIX 5.1).
From high-speed, team-based PCB design environments and silicon-package-board co-design, to the latest in personal productivity - Cadence offers an extensive range of industry-standard PCB solutions to accommodate your specific needs.
The new PSD 15.0 PCB and IC Packaging design solutions release addresses the growing complexity and speed of today's leading-edge PCB designs. Enhanced to address the monumental challenges of integrating nanometer-scale ICs into packages, onto boards, and into systems, the release includes new capabilities that allow engineers to effectively design and analyze the high-speed system interconnect. Advances in packaging technology automate and improve the design of stacked-die packages to support the growing system-in-package market. Productivity enhancements across the flow help customers get products into volume production faster.
15.0 is supported on the following platforms: Windows (2000, and XP Pro), Sun (Solaris 7 and 8), HP (HP-UX 11.00 and 11.11), and IBM (AIX 4.3.3).
CONCEPT HDL
The Hierarchy Viewer window displays the complete hierarchy of a design. The key benefit of this new feature is the ability it gives you to navigate through a design and reorder modules in the hierarchy.
New Global Modification support in Concept HDL enables you to delete or modify any net, pin, or component property from a design. It also allows you to globally replace one component with another-across a complete design. You can choose the new component by choosing from a list in Physical Part Filter dialog box or by picking a replacement from the existing components in the design. Component change is also supported in the logical mode.
In Concept HDL 15.0, the Assign Power Pins GUI provides efficient handling and creation of power pin properties. This graphical environment allows you to easily define new power pins without having to search for the names and numbers of pins in the chips.prt file or the .ptf file. The Power Group GUI displays a list of global signals, allowing you to easily select any global signal. By default, the properties defined on the schematic have priority over those defined in the chips.prt and .ptf files, however you can set the ALLOW_POWER_PINS directive to reverse the priority.
ALLEGRO
The positive shapes project completely redefines shape creation, editing, voiding and parameter setup in Allegro. Dynamic shapes support real-time plowing, voiding and healing. Allegro 15.0 also introduces new shapes parameters. The separate shapes editing and creation environment has been eliminated. Other enhancements include: Improved graphics, a separate shape grid, island checking and nesting make shape use more productive, intuitive and powerful.
Differential Pair Overhaul
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The Differential Pair project overhauls and adds new technology and functionality for differential pair creation, routing, editing, constraint management, and DRC checking. Differential Pair constraints can now be applied through ECSets, or net-level properties in Constraint Manger. Visual DRC aids provide feedback on differential pair violations including: uncoupled segments and phase control. Interactive etch editing now routes both nets of a differential pair simultaneously while adhering to differential gap width rule. Trace editing commands have also been modified to support differential pair traces. Tools such as an Impedance Calculator and Differential Pair Generator can eliminate manual processes.
Updates to testprep focus on enhancements that add new features along with improving the User Interface and reporting capability. New features-such as a test fixture sub-class layer and the ability to interactively add test points directly to a trace-make manual editing easier. New test point DRC checks have been added as well as several DRC updates. Test point reports and properties have also been enhanced. A new testprep user interface affords greater control over the test point functionality.
SPECCTRA
Layer Set functionality provides the ability to define routing layer "sets" and use them to control routing. Designers have the need to define a number of layer pairs that they prefer to route certain nets or busses on and restrict routing from layers not in the "set". This is usually related to the similar impedance values of those particular layer sets. Similar to Use Layers, you can now assign Layer Sets to a Class, Group Set, Net, or Group.
Virtual Pin (T-Points) Functionality
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The way SPECCTRA handles virtual pins has been improved. In the past, designers would get the best results by moving the T-Points to the desired location in Allegro, applying a Fixed T Tolerance in order to save the location, and forcing SPECCTRA to route to the virtual pins at the predetermined locations.
The dynamic movement of virtual pins has been enhanced in 15.0, so you can allow SPECCTRA to determine the location for virtual pins, eliminating the need to move T-Points in Allegro. By not applying a Fixed T Tolerance, you can let SPECCTRA determine the location for virtual pins and allow the router to dynamically move them if necessary during later routing passes. You can still pre-place critical T-Point locations if you wish, by applying the Fixed T Tolerance and then let SPECCTRA do the virtual pin placement for the less critical nets.
Alignment with Allegro's New Differential Pair and Dynamic Shapes Functionality
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SPECCTRA is aligned with and fully supports Allegro's new differential pair functionality, making these new constraints available for nets, classes, groups, groupsets, and fromtos. SPECCTRA also supports Allegro's dynamic shapes, allowing for user control of via pop through a shape, and wire plow during fanout.
SPECCTRAQUEST
In Release 15.0, Constraint Manager supports the high-speed differential pair flow by letting you capture differential pair constraints, analyze differential pair circuits, and promote design intent directly to the layout. Also in this release, round-trip differential pair topology editing is realized. You can extract a differential pair topology, perform what-if analysis in SigXplorer, specify differential pair constraints directly in SigXplorer, then update the topology to Constraint Manager, which in turn updates the constraints applied to the layout through a referenced ECSet.
Related simulation changes include the ability to apply a differential custom stimulus at the board level and support for erential buffer delays including the ability to assign an ESpice model as a test fixture in their computations. SigXplorer captures differential custom measurements and differential stimuli in a topology file, which can then be promoted to Constraint Manager and applied to the design as an ECSet.
HSPICE-to-IBIS in Model Integrity
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Many IC companies develop and distribute IO buffer models as encrypted HSPICE models. Although you can run these HSPICE models using the HSPICE engine, Model Integrity's new HSPICE-to-IBIS conversion module lets you create IBIS models from SPICE output (.lis) files.
Proven curve fitting and data extraction algorithms, used in the HSPICE to IBIS model creation process, were developed in partnership with a leading semiconductor manufacturer who has generated hundreds of IBIS models over the last 10 years. These algorithms provide helpful functionality, including the identification of SPICE I-V and V-t tables for the creation of process corners as well as the recognition of buffer type. Additionally, it provides intelligent best points table reduction, clamp current subtraction, on-die termination identification, and model scaling.
SPECCTRAQuest Power Integrity
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Release 15.0 provides a number of significant enhancements to SPECCTRAQuest Power Integrity. In the area of multi-node simulation, you can now optionally generate an HSpice version of a plane model. All multi-node simulations now include dielectric loss parameters. In multi-mode simulation mode, Power Integrity now computes values for fd (measurement frequency) and g (dielectric shunt conductance). For increased accuracy, you can now place the noise source anywhere on a component and it will follow the component if you move it. You can also edit the noise source subcircuit as well. A number of other usability enhancements were also made.
ADVANCED PACKAGE DESIGNER/ADVANCED PACKAGE ENGINEER
New Auto Wire Bond Editing Tools
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A completely new, automatic wire-bond editing environment has been added to IC Packaging design environment in release 15.0. Targeted at the challenges presented by Systems in Package (SiP) technology, the new wire-bond tools give you a level of functionality that can handle the complex wire-bond patterns that are inherent in this technology. This includes Support for stacked die, separate bonding tier controls, route escapes, and more.
Differential Pair Routing and Editing
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The number of differential pair nets on a single package design has exploded. Today, it is not uncommon to see to more than 50% of the nets defined as differential pairs. This has created a difficult challenge for package designers charged with the task of routing these differential nets in a timely manner while keeping an eye on package complexity and cost. Cadence's new Differential Pair routing tools directly address this challenge by providing a number of capabilities, including tandem differential routing, group slide, heads-up display, differential pair calculator, differential constraints, and new routing options.
New Dynamic Shapes Environment
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The shapes editing environment has been completely re-written to provide the user with the capability to dynamically create and edit complex shape patterns quickly and easily. These changes include shapes as part of the main design window, dynamic shape creation and voiding, plowing and healing, as well as hierarchical parameter control.
Spider Route Improvements
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The 15.0 release includes enhanced Spider Route for flip chip and multi-row bond patterns. This expanded capability includes support for flip chip die, including both peripheral and full-matrix die as well as a separate constraint area under the die where tight pad pitches require tighter routing rules.
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