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Home > Products > System-in-package design > Design tasks
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System-in-package design design tasks
|  | RF SiP Design
While system-in-package (SiP) design makes it possible to combine RF and analog content on the same substrate, it presents a number of challenges. These include designing and integrating RF/analog chips with substrate-level buried RF passive devices as well as enabling top-level pre and post-layout circuit simulation of the entire SiP design. Cadence® SiP RF Architect provides the proven path between analog design and simulation and SiP RF layout. It enables designers to create a single, system-level, circuit simulation-ready schematic for RF/analog die, SiP substrate, and packaged and embedded discretes. | | | Digital SiP Design
System-in-package (SiP) implementation poses new hurdles for system architects and designers. Increasing the number of IC die not only introduces more overall complexity, but these die sharing the same power grid within a package substrate also makes power delivery and signal integrity more complex. Packing more functionality into a smaller footprint often involves highly complex combinations—such as stacked die, wirebond die stacked on flip-chip die, direct die-to-die attachment, and others—which makes the capture, prototyping and optimization of the SiP's connectivity a major challenge. Additionally, system engineers require a new set of solutions that address the specific challenges involved in integrating signal integrity (SI) analysis, interconnect extraction, and modeling with the physical SiP design environment. |
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