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Home > Products > System-in-package design > Design tasks > RF SiP Design
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RF System-in-package design
While system-in-package (SiP) design makes it possible to combine RF and analog content on the same substrate, it presents a number of challenges. These include designing and integrating RF/analog chips with substrate-level buried RF passive devices as well as enabling top-level pre and post-layout circuit simulation of the entire SiP design. Cadence® SiP RF products and methodology kit provide the technology, methodologies, flows, and more to help designers overcome these challenges.
 | Cadence RF SiP Methodology Kit
Enables fast and streamlined adoption of RF SiP design techniques by leveraging new SiP technologies and verified advanced methodologies for RF SiP design. The kit enables wireless design teams to have predictable design schedules by increasing design productivity and quality influencing first-pass success. The Kit delivers verified methodologies and flows demonstrated on a segment representative design.
| | Cadence SiP RF Layout
Provides the proven path between Virtuoso® analog design/simulation and substrate layout. It enables layout designers to implement a SiP RF design that included RF/analog die, embedded RF discretes, constraint driven interconnect routing as well as full SiP tapeout manufacturing preparation.
| | Cadence SiP RF Architect
Provides the proven path between Virtuoso® analog design/simulation and SiP RF layout. It enables designers to create a single, system-level, circuit simulation-ready schematic for RF/analog die, SiP substrate, and packaged/embedded discretes.
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