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Home > Products > System-in-package design > Products > Cadence SiP Digital Layout
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Cadence SIP Digital Layout
While system-in-package (SiP) design allows electronics makers to pack more functionality into a smaller footprint, it often involves highly complex combinations, such as stacked wirebond die, wirebond die stacked on flip-chip die, direct die-to-die attachment, and others.
Cadence® SiP Digital Layout addresses this complexity by providing a complete constraint and rules-driven package substrate layout environment that supports all packaging methods, including PGA, BGA, micro-BGA, chip scale, as well as flip-chip and wirebond attach methods.
Cadence SiP Digital Layout is available in a GXL (PDF) offering.
Key benefits
 | Provides 3D die stack creation/editing for rapid stack assembly and optimization | | Enables IC I/O pad ring/array co-design and connectivity optimization at the IC, substrate, and system levels | | Allows connectivity assignment and optimization between ICs and substrate for optimized/minimal layer usage based on signal integrity and routability | | Reduces tedious, time-consuming, and manual breakout editing via flip-chip die autoroute-breakout | | Includes comprehensive substrate DFM capabilities for rapid design manufacturing preparation | | Provides 3D design viewer and DRC for accurate full 3D wire bondability verification, design review debug, and design documentation for assembly and test |
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