Cadence SIP RF Architect
While system-in-package (SiP) design makes it possible to combine RF and analog content on the same substrate, it presents a number of challenges. These include designing and integrating RF/analog chips with substrate-level buried RF passive devices as well as enabling top-level pre and post layout circuit simulation of the entire SiP design.
Cadence® SiP RF Architect provides the proven path between Virtuoso® analog design/simulation and SiP RF layout. It enables designers to create a single, system-level, circuit simulation-ready schematic for RF/analog die, SiP substrate, and packaged and embedded discretes.
Cadence SiP RF Architect is available in an XL (PDF) offering.
Key benefits
Provides a single, top-level Virtuoso schematic and simulation driven environment for RF ICs, SiP RF module substrate, and embedded RF passive elements
Supports bi-directional ECO and LVS flow between RF design team and SiP RF module layout team
