Cadence SIP RF Layout
While system-in-package (SiP) design makes it possible to combine RF and analog content on the same substrate, it presents a number of challenges. These include designing and integrating RF/analog chips with substrate-level buried RF passive devices as well as enabling top-level pre- and post-layout circuit simulation of the entire SiP design.
Cadence® SiP RF Layout provides the proven path between Virtuoso® analog design/simulation and substrate layout. It enables layout designers to implement a SiP RF design that includes RF/analog die, embedded RF discretes, constraint driven interconnect routing as well as full SiP tapeout manufacturing preparation.
Cadence SiP RF Layout is available in a GXL (PDF) offering.
Key benefits
Provides bi-directional engineering change order (ECO) and layout versus schematic (LVS) flow between RF design team and SiP RF module layout team
Supports substrate-level RF passive P-cell through Virtuoso top-level-driven design
Allows direct import of SiP substrate-ready IC die footprints from Virtuoso Layout Editor
Speeds die stack assembly and optimization with 3D creation/editing
Provides IC I/O padring/array co-design and connectivity optimization at the IC, substrate, and system level
Allows signal integrity (SI) and routability-driven connectivity assignment and optimization between ICs and substrate for optimized/minimal layer usage
Reduces tedious, time consuming manual breakout editing via flip-chip die autoroute-breakout
Includes comprehensive substrate DFM capabilities for rapid design manufacturing preparation
Features 3D design viewer and DRC for accurate full 3D wire bondability verification, design review debug, and design documentation for assembly and test
