Cadence Design Systems, Inc.
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Incisive functional verification
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Encounter digital IC design
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Encounter RTL Compiler
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Encounter Timing System
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NanoRoute
VoltageStorm
Cadence QRC Extraction
Cadence Chip Optimizer
Cadence SiP Digital Architect
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Cadence SiP Digital SI
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Applications Using the ARM Cortex-A8 Processor
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Cadence Chip Optimizer
Cadence Space-Based Router
Cadence QRC Extraction
Virtuoso Analog ElectronStorm Option
Virtuoso Analog VoltageStorm Option
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Assura DRC
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Cadence SiP RF Architect
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Cadence RF SiP Methodology Kit
Cadence SiP RF Architect
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Cadence SiP Digital Architect
Cadence SiP Digital Layout
Cadence SiP Digital SI
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Assura DRC
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Cadence CMP Predictor
Cadence Litho Electrical Analyzer
Cadence Litho Physical Analyzer
Cadence MaskCompose Suite
Cadence QuickView Viewer
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Diva Physical Verification
Dracula
Encounter Test
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Applications Using the ARM Cortex-A8 Processor
Chip Planning and Silicon Virtual Prototyping
Advanced verification
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