Advanced Packaging Solution
As semiconductor makers strive to satisfy fierce consumer demand for the latest electronic innovations, they are moving to nanometer-scale chips that contain more functionality and deliver higher performance than ever before. In turn, IC package designers are under intense pressure to keep pace.
At the same time, packaging technology itself is undergoing rapid change, including the move to multi-layer flip-chip packaging to accommodate 1000+ I/O pins and multiple stacked die systems-in-package (SiP) designs, which often provide a viable alternative to SoC implementations. In addition to reduced cost, lower power, and higher performance, SiP design offers the flexibility to mix RF and high-speed digital circuitry in the same package. However, this also means it requires expert engineering talent in widely divergent fields.
Cadence addresses these challenges with a robust set of capabilities targeted specifically at current and future packaging technologies, including wirebond, perimeter array flip-chip, full array flip-chip, and stacked multi-die packages. The unique Cadence approach to advanced IC packaging breaks through the accepted ad hoc system of isolated job tasks and expert engineering. The result is package/board co-design for end products that are optimized for size, cost, and performance.
The Cadence Advanced IC Packaging solution includes:
 | IC/package co-design — combines chip-level I/O feasibility planning capabilities with industry-leading IC package tools to deliver a proven co-design methodology integrated with Cadence® First Encounter® | | IC/package modeling and extraction — allows engineers to make tradeoffs among electrical and physical design requirements to meet cost and performance targets | | Wirebond package design — enables dynamic real-time push-shove wire creation and editing, which allows engineers to rapidly create bond tiers and wire groups that meet assembly and routing needs. Includes automated power and ground ring creation along with die flag speed over all IC bondout processes | | SSO/SSN pre-simulation — provides package designers with the upfront ability to predict the acceptable ratio of power/ground connections per signal to minimize power/ground noise while evaluating package routability for signal traces exiting the IC die | | IC/Package power delivery modeling (dynamic IR drop) — enhances engineers' ability to make critical decisions regarding physical interconnect and substrate technology to improve overall performance of signals and the package power delivery system | | RF module design — enables designers to create a single, system-level, circuit simulation-ready schematic for RF/analog die, SiP substrate, and packaged/embedded discretes | | Multi-die stacked digital SiP co-design — optimizes system connectivity/functionality between ICs, SiP package substrate, and target PCB system through a concurrent co-design methodology and process | | RF SiP Methodology Kit — enables fast and streamlined adoption of RF SiP design techniques through verified methodologies and flows demonstrated on a segment representative design within the RF SiP Methodology Kit |
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