|
Analysis and signoff
The Digital Implementation solution from Cadence provides a complete and unified
analysis environment for signoff-driven implementation, optimization, and final signoff,
accounting for the interdependencies of logical, physical, electrical, and manufacturing effects.
As process technologies continue to shrink, new design and analysis challenges
arise that impact manufacturing predictability and strain conventional signoff analysis solutions.
Designs that pass traditional signoff standards might still fail in silicon, while guardbanding
or over-conservative margins to satisfy traditional static timing analysis (STA) signoff can
negate the benefits of smaller process geometries
The Digital Implementation solution delivers the most comprehensive and accurate
analysis and signoff solution. It brings together logical, physical, electrical, and
manufacturing domain requirements in a single, easy-to-use environment, enabling front-end
to back-end design handoff, signoff-driven implementation, and final signoff. The
Digital Implementation solution offers a complete debug environment for timing, signal
integrity, power, concurrent multi-corner, statistical, electromigration, and thermal analysis.
It allows for quick and easy multi-dimensional root-cause analysis to reach design closure
and time-to-volume production much faster. Designers can prevent silicon failures and better
manage variations-across both a wafer and the surface of a single chip.
Key differentiators
 |
Complete and unified analysis environment (timing, signal integrity, power,
statistical, thermal, electromigration)
| |
Consistent, integrated, and standalone signoff solution for faster design
convergence and time-to-volume production
| |
Industry's leading statistical static timing analysis (SSTA) and thermal
analysis solution
| |
Significant reduction in signal integrity pessimism to achieve faster design closure
| |
Accurate dynamic power grid analysis to enable precise decoupling capacitance insertion
| |
Interface to Encounter® Conformal® Constraint Designer for constraint
validation and false-path elimination
| |
Interface to model-based verification (MBV) and DFM impact on timing, signal integrity, and power
| |
Better productivity/usability with intuitive GUI, global timing debug, and built-in critical path
SPICE simulation
| |
Physical layout viewer and what-if analysis with multi-view cross-probing
| |
Industry's most comprehensive and accurate effective current source model
(ECSM) library and characterization for timing, signal integrity, power,
and statistical analysis
|
White papers
Press releases
Articles
Online demo
Products
Cadence Designer Network
| |
