Digital Implementation solution
With ever-growing demand for more functionality and greater performance in electronic devices, semiconductor makers face a whole new class of challenges. In addition to increasing complexity—due to enormous instance counts (3M+), huge numbers of macros (300-500), multiple functional modes (4-5 becoming routine), and other factors—engineers need to deal with tighter time to market and yield-sensitive nanometer designs. Companies must also overcome all these hurdles with a given budget and given number of engineers.
Digital implementation teams require a new approach that addresses a range of issues related to high-capacity, high-performance SoC designs at 65nm nodes and below. Power, which few designers worried about at 180nm, is now a mission-critical concern. Designs must not only incorporate the latest power management in the logic design phase, but these techniques need to be automated during the implementation phase.
Moving to 65 and 45nm also creates other concerns, such as statistical variations across the wafer and manufacturability issues. In addition, today's large chips also typically combine analog and digital circuitry, and to be productive designers need the ability to address both types of design tasks in the same environment.
The Digital Implementation solution from Cadence provides the speed, ease-of-use, automation, and silicon accuracy designers need to achieve success with extremely complex digital ICs. It is ideal for:
 | Low-power design — Enables designers to control power, timing, and area tradeoffs from the RTL design phase, while ensuring continuous convergence during implementation | | Implementation of large-scale designs — Replaces conventional "divide-and-conquer" approaches with a scalable and integrated environment for more efficient and cost-effective implementation of large-scale designs | | Design for Manufacturing — Offers accurate modeling of variations and critical area analysis based on the process technology node up front. It also delivers a full array of CMP- and lithographically-aware yield enhancements, such as high-yield cell optimization, double cut via insertion, interconnect widening and spreading, and density uniformity optimization | | Mixed-signal design — Provides a complete synthesis and place-and-route system for small digital block implementation in the context of an analog-driven, mixed-signal design methodology |
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