Low power
Logic design
Advanced verification
Digital implementation
Low power
Analysis and signoff
Physical implementation
Custom design
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Digital implementation solution News and Events

This page contains press releases, articles, and events related to Digital implementation solution.

Press releases



01/29/07Cadence Delivers Industry's First Complete Low-Power Solution; Leverages Si2-Approved Common Power Format
10/26/06Freescale Continues Successful Migration to Cadence Encounter Test
10/23/06Cadence Logic Design Team Solution Addresses Front-End Design 'Predictability Crisis'
10/02/06Cadence Develops Lithography-Aware Design Flow in Collaboration with Brion and Clear Shape
09/07/06Cadence and SMIC Deliver 90-Nanometer Low-Power Solution for Energy-Efficient SoCs
09/05/06Cadence Announces Encounter Timing System for Advanced Timing Signoff Analysis
allpress releases

Articles

12/19/06Cadence claims RTL synthesis boost
10/01/06Qualcomm, Cadence implement DFT for CDMA devices
09/05/06Cadence rolls 'signoff quality' timing analysis
09/01/06An overview of on-chip compression architectures
07/06/06Save Those Watts With a Power-Aware Design Flow for SoCs
06/22/06Initiative Looks To Establish Low-Power Design Infrastructure
all articles