Incisive transaction-based acceleration
Incisive® transaction-based acceleration (TBA) helps design and verification teams reduce their verification time by providing co-emulation between Incisive simulation and Incisive acceleration and emulation. With Incisive TBA, teams benefit from a 100x—1000x increase in performance over RTL simulation, direct links to simulation, and a highly productive simulator-like environment. Incisive TBA is compatible with the SCE-MI 1.1 standard, but its many enhancements take productivity to a much greater level.
TBA is fully supported by the Incisive Simulator and both the Incisive Palladium® and Xtreme® series of accelerators/emulators. The same SystemC transaction-level models (TLMs) used for system-level design and as reference models for RTL development can be used in conjunction with RTL acceleration.
Central to TBA's effectiveness is the Cadence unique congruency feature, which ensures the same results in simulation and acceleration without needing to change any design or testbench models. This results in faster debug and an overall reduction in verification time. Other features:
 | Timed testbenches allow users to control the occurrence of specific critical events in the testbench during a specified timed interval | | Streaming mode quickly optimizes a testbench for performance, which is ideal for regression mode operation | | Reactive mode can greatly improve debug speed and reduce turnaround times | | A transaction viewing window shows source code, transactional data, and waveforms in one comprehensive window for faster debug | | A TBA performance profiler highlights any performance bottlenecks and points the user to where they need to modify their testbench to achieve the highest possible performance |
The Incisive TBA methodology supports the Incisive verification IP (VIP) library of specific protocols such as PCI Express, Ethernet, AHB, and AXI. The Incisive VIP library delivers fast RTL simulation and high-speed accelerated hardware mode with a single transactor for both environments. These same transactors support a high-speed simulation interface for architectural modeling at the transaction level or high-level software development.
Resources
EE Times article: Transaction Models Offer New Deal for EDA
Incisive newsletter  | Article 6: An Integrated block Level Verification Approach from Simulation to Co-emulation | | Article 7: Leading Edge Transaction-based Acceleration Methodoogy |
Webinar: Leveraging Transaction-based System Verification to Increase Productivity, Predictability, and Quality
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