Logic Design Team Solution
With stricter scheduling adding to timing and area challenges, the job of logic design teams has become increasingly difficult. Compounding these existing hurdles, logic design teams face an array of emerging challenges as designs increase in complexity and as shrinking geometries create new considerations in front-end design. Among these new concerns are the need for fast and early verification, criticality of power affecting functional design, logic-physical effects, testability, front-end handoff, and the ad-hoc and highly iterative nature of the design process itself—all of which can lead to unpredictable project schedules.
Recognizing the need to inject predictability into the RTL design process, Cadence has developed a fundamentally new approach to front-end design. The Cadence® Logic Design Team Solution for the first time offers logic design teams an early and comprehensive concurrent metrics-driven approach to front-end design. It enables logic design teams to effectively design, verify and implement their RTL block and chip-level designs without the risk of destabilizing their existing design and verification process.
The solution raises the level of front-end automation and concurrencies and reduces the schedule variability risk faced with complex designs using today's iterative and serial ad-hoc approaches.
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An innovative integrated environment combines design, early verification and front-end implementation tasks into a set of objective-focused sub-flows, and automates the concurrent management of progress toward the design goals. The architecture includes the following components:
 | Design with Verification – delivers on the promise of early design verification and power management by design teams in an integrated approach starting with an extended-assertion based formal analysis solution, power-aware simulation and acceleration, and verification management | | Design with Power – brings the first power-aware, integrated and managed designer verification and front-end implementation solution for RTL design coupled to the extended verification flow, and throughout implementation.
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| | Design with Test – provides a seamless integration with the logic design process to develop high-quality test infrastructure with minimal iterations.
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| | Design with Physical – reduces logic-physical iterations by providing accurate estimates of timing using the actual physical engines used in implementation in a logic design environment.
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| | Design Logical Signoff – enables a holistic backend handoff check for static timing, equivalence, and timing constraints for design teams to verify front-end closure with predictability and confidence.
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| | Design Management – provides an automated plan and metrics-driven management solution that tracks progress of the evolving design against all its functional, performance, and schedule objectives together, bringing unparalleled predictability from plan to closure
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The synergistic combination of these elements enables resolution of design challenges earlier—on a unified "Designer's Desktop"—to reduce iteration and take the guesswork out of project schedules.
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