Low power
Logic design
DESIGN TASKS
Plan-to-Closure Methodology
Assertion-based verification
Low-power design flow
Transaction-based acceleration
Verification of ARM processor-based designs
Applications Using the ARM Cortex-A8 Processor
Chip Planning and Silicon Virtual Prototyping
Advanced verification
Digital implementation
Custom design
PCB design
Advanced packaging
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Cadence Logic Design Team Solution News and Events

This page contains press releases, articles, and events related to Cadence Logic Design Team Solution.

Press releases



04/15/08IDT Uses Cadence Encounter Conformal Constraint Designer to Accelerate Time To Market
04/07/08STARC Adopts Cadence Encounter Timing System as its Static Timing Analysis Signoff Solution
04/07/08Seiko NPC Sees a Big Productivity Boost in DFT Design Flow with Integrated Cadence Test and Synthesis Technologies
12/04/07Cadence Marks 100th Customer Adoption of Encounter Timing System
10/23/07Cadence Test Technology Helps LSI Corporation, Kawasaki Microelectronics Deliver Products Faster
10/23/07Cadence Encounter Test Helps Enable IBM To Deliver High-volume Chips
morepress releases

Third-party press releases



06/10/08ASSET works with Cadence to drive embedded instrumentation for deep analysis of complex ICs
03/11/08New ARC Energy PRO Core Family Slashes Power Consumption By Up to 75%
allthird-party press releases

Articles



06/12/082007 International Test Conference papers
05/06/08How floorplanning guides synthesis and physical design
04/22/08What floorplan information is needed for synthesis
04/17/08Cadence Announces Reentry Into Upstream Design in Japan
03/31/08Tool Automates Engineering-Change-Order Generation
more articles

Webinars



12/06/07Archived Webinar: Logic Designers: Recapture Control to Achieve Predictable Closure on Your Project Goals
09/26/07Archived Webinar: New Approach to Logic Design: A Shift in the Paradigm from Design for Test to Design with Test