Cadence Design Systems, Inc.


	DESIGN TASKS


		Plan-to-Closure Methodology


		Assertion-based verification


		Low-power design flow


		Transaction-based acceleration


		Verification of ARM processor-based designs


		Applications Using the ARM Cortex-A8 Processor


		Chip Planning and Silicon Virtual Prototyping

Technical Info

This page contains technical information related to Cadence Logic Design Team Solution.

Logic Design Team Solution White papers

Model-based Methods Critical for Effective Manufacturing-aware Physical Design
Next-Generation Signoff Analysis Tackles Electrical, Physical, And Manufacturing Challenges
Design with Physical: Bringing Predictability to Logic Design
Architecting, Designing, Implementing, and Verifying Low-Power Digital Integrated Circuits
Complete Timing Signoff in the Nanometer Era
Design with Test
Front-End Logic Design: Taking the Risk out and Putting Schedule Predictability in
all white papers