Low power
Logic design
DESIGN TASKS
Plan-to-Closure Methodology
Assertion-based verification
Low-power design flow
Transaction-based acceleration
Verification of ARM processor-based designs
Applications Using the ARM Cortex-A8 Processor
Chip Planning and Silicon Virtual Prototyping
Advanced verification
Digital implementation
Custom design
PCB design
Advanced packaging
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Verification of ARM processor-based designs

With unforgiving market windows and ever-increasing demand for more functionality and performance packed into single chips, design and verification engineers face a paradox within various market segments such as wireless and consumer. Delivering better products requires incorporating new technologies and, as a result, adds risk to the design and verification process. To reduce risk, achieve predictable verification closure, and deliver innovative products on time, engineers need automated verification process management, IP reuse, and the latest verification technologies.

The Cadence® Functional Verification Kit for ARM offers a comprehensive verification solution specifically for engineers developing ARM® processor-based designs. The Kit contains ARM processor-based verification methodology and flows, a segment representative design, verification process automation (VPA) technology, and reusable verification IP (VIP). The proven Incisive Plan-to-Closure Methodology from Cadence has been tailored specifically to ARM processor-based designs.

The Cadence Functional Verification Kit for ARM contains documented best practices, "golden" executable examples, and libraries (building blocks and utilities commonly required for SoC design and verification). The Kit also includes a comprehensive portfolio of customer-proven verification IP that consists of executable compliance verification plans; AMBA® assertions for formal analysis, simulation, and acceleration; advanced simulation-based testbench components; transaction-based components for simulation and acceleration; and an ARM926™ Logic Tile prototype hardware board for in-circuit emulation.

Design and verification teams can use the segment representative design as a basis to understand the recommended methodologies, and then map the demonstrated techniques, technologies, and verification IP to their own designs. This provides a proven and realizable plan to improve their verification process. With this step-by-step approach, teams can absorb and understand a wide array of technologies that optimize the verification solution they need and address the unique challenges they face in verifying ARM processor-based designs.

The Cadence Functional Verification Kit for ARM relies on and integrates with the following technologies (not included):

Incisive Plan-to-Closure Methodology
Incisive Enterprise Manager
Incisive Enterprise Specman® Simulator
Incisive Enterprise Specman Elite®
Incisive Enterprise Scenario Builder
Incisive Palladium® series
Incisive Design Team Manager
Incisive Design Team Simulator
Incisive Formal Verifier
Incisive Xtreme® series


Cadence Functional Verification Kit for ARM