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The Physical Design Challenges
Three key design challenges are discussed here:
Chip assembly predictability
To provide a physical design integration solution for mixed-signal macrocells through large mixed-signal systems-on-a-chip (SoCs), the design flow must accept IP across multiple design domains. The physical design process is always at the end of a tight schedule and squeezed to meet tapeout schedules. To meet this challenge, the full-chip assembly and verification process must be highly predictable, especially in the final weeks before tapeout. This is not the time to find routing or verification issues. As a result, the best approach is to rely on continuous evolution, wherein the design is built continuously as new block configurations are passed to it. Continuous evolution is to physical design as
continuous regression simulations are to simulation and verification. This approach is the key to meeting a schedule. When executed, last-minute changes are effectively added to a known process, ensuring a predictable design schedule. Problems are caught early on during the first several builds, when there is time to deal with them.
Chip integration speed and accuracy
Custom design teams need a design methodology that combines the speed of top-down design with the silicon-accuracy of bottom-up design approaches—as they face greater market demands, tighter schedule, and ever increasing design complexity and physical effects. This requires a pragmatic "meet-in-the-middle" approach. A key element in the design process for mixed-signal ICs, the chip integration flow encompasses floorplanning, routing, optimization, physical verification, chip finishing, and through to tapeout. It accepts IP across multiple domains of analog, digital, and RF, and
can be applied to a complex integration or a particular domain area.
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Virtuoso chip integration flow
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The chip integration flow can be applied to two scenarios. The first is creating macrocell with digital content as well as several full-custom blocks, for delivery to a larger SoC. The second scenario is a full chip consisting of several analog blocks and a small number of digital blocks, in which the digital blocks can be quite large. To find out more about how to meet today's design challenges, click here  for The Chip Integration Flow White Paper. You can also view a product demonstration of the tools in this flow—select Virtuoso Custom Design Platform
Rapid migration to a new process technology
Layout is a significant time sink for a design team, so the ability to reuse hard IP through efficient migration offers a significant productivity gain. Designs are often alternated between technology nodes amongst different foundries and/or processes. Often, there is a need to migrate from one process technology to another in order to perform some or all of the following: meet a higher clock speed with a technology shrink, lower power requirements, reduce die size and reduce chip cost. This process of migrating IP requires a careful and controlled process. The Virtuoso Layout Migrate tool provides the necessary control and automation to rapidly move designs to new process technologies.
Learn more about Process Migration by attending the Virtuoso Layout Migrate class. Check out the complete list of Education Services courses.
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