Cadence Design Systems, Inc.

Type: Webinar Date: Archives now available

Couldn't attend Cadence® Technology on Tour demo sessions? Missed any demos at CDNLive!?

Here's your opportunity to see the demos you may have missed or to view your favorite demos again. Attend our free Technology on Tour demo webinar series every Tuesday, Wednesday, and Thursday at 10:00am Pacific Time from September 26 through November 14!
Click on the topic below that interests you most for demo descriptions and to register now!

• Functional verification
• Digital IC design
• Custom design
• Silicon-package-board co-design
• System-in-package (SiP) design
• Wireless IC Design

• Combine automation management, simulation, formal analysis, and acceleration technologies with a proven methodology that takes RTL design teams from assertions and verification plan to closure
• Jump-start your verification process—save time and reduce risk by using pre-verified verification IP (VIP) modules
• Optimize yield for 65nm designs, speed design closure, and achieve faster time to tapeout on complex nanometer designs with SoC Encounter™ system
• Address power consumption challenges—run through a number of low-power techniques with the Encounter® low-power design flow
• Use Cadence Chip Optimizer and Cadence Space-based Router for leading-edge, full-chip, mixed-signal routing and DFM/DFY optimization at sub-65nm
• Benefit from improved usability, productivity, design reuse, accelerated time to market, and yield optimization with the new Virtuoso® platform design environment
• Accelerate physical implementation with the new Virtuoso Layout Suite's advanced automation capability
• Produce intelligent, navigable, traversable PDF files from schematics with Allegro® Design Publisher
• Obtain higher performance and use less power and PCB real estate with DDR2 design-in IP
• Enable AMS chip designers to implement circuit-simulation—driven SiP RF module design that includes RF/analog die, embedded RF discretes, post-layout parasitic extraction, constraint-driven interconnect, and full SiP tapeout manufacturing preparation
• Use a unique environment to explore, define, and optimize system connectivity through multi-chip I/O pad ring/array co-design, optimizing connectivity between ICs, SiP substrates, and target PCB systems
• And more!

• Designers and design management
• Engineers and engineering management
• Verification engineers and management
• PCB designers
• IC package designers and IC package design management
• System architects responsible for complete system specification

Questions about this event?



Send email to events@cadence.com