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ADVANCED NODE DESIGN
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If you're designing for a leading-edge semiconductor process, you already know that design tools are evolving to handle the manufacturability challenges of smaller transistors and wires, as well as the data volume and complexity challenges of denser and more complex chips. Even if you're not targeting a leading-edge process today, changes in the product design environment will benefit you.
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No matter which process node companies use, design complexity and scale
continue to escalate. In fact, the International Technology Roadmap for
Semiconductors 2006 Update predicts that the amount of digital logic on
a typical consumer-product ASIC will double every three years through
2020. Cadence addresses this challenge by delivering customers an Advanced
Node Design solution with the capacity and speed required to handle large
designs on the newest process nodes. These enhancements also improve team
productivity and project predictability for large complex chips on any node.
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At 65nm and below, manufacturability challenges also become numerous
and widespread. To mitigate risk of customers designing at advanced
process nodes, the Cadence Advanced Node Design solution addresses
varied manufacturability considerations into the early stages of design
flow. Though less widespread, similar manufacturability risks can affect
aggressive designs in larger manufacturing processes like 90nm. By
integrating comprehensive DFM analysis into the design flow, the
production-proven Cadence solution also optimizes designs to prevent
downstream problems, design respins, and potential yield risks at any
modern process node.
Cadence also delivers a broad array of leading custom IC solutions,
which have proven to help customers accelerate volume production of large,
complex designs at advanced node processes of 65nm and below. These
technologies provide tighter manufacturability integration, improved
yield and parasitic analysis and performance-boosting simulation tools
for accurate and efficient verification of designs.
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Virtuoso Custom Design Platform
The Cadence Virtuoso® custom design platform, the industry's
leading solution for analog and mixed-signal design, extends the
custom design solution to enable concurrent design and manufacturing
awareness to be applied throughout the design flow, leading to
shorter time to yield for advanced node designs.
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Virtuoso Spectre Circuit Simulator
A production proven and industry-leading analog SPICE circuit
simulator with well-established comprehensive foundry support,
Cadence Virtuoso Spectre® Circuit Simulator now includes
new "turbo" technology. This boosts performance by 5 - 10X while
ensuring silicon accuracy, enabling designers to efficiently and
effectively verify their designs.
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NanoRoute®
The innovative architecture and superthreading technology in NanoRoute® enable
design of very large chips, while its SMART technology holistically addresses
timing, area, power, and manufacturability constraints during physical
implementation of the most complex SoCs.
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Encounter® Timing System
From front-end logic design through back-end digital implementation, the
Encounter Timing System provides a silicon-accurate common timing engine with
advanced capabilities like signal integrity, thermal analysis, low-power design,
and statistical static timing analysis.
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Cadence QRC Extraction
Accurate parasitic extraction is the foundation for accurate timing and
simulation, and Cadence QRC Extraction includes the full spectrum of
technologies for all nanometer-scale design styles, including RF, analog,
mixed-signal, custom digital, and cell.
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SoC Encounter
Digital design flows for advanced process nodes require a complete RTL-to-GDSII
solution like SoC Encounter that includes RTL synthesis, silicon virtual
prototyping, automated floorplan synthesis, clock network synthesis, design for
manufacturability, mixed-signal support, and nanometer routing.
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Design for Manufacturability
Design for manufacturability technologies are integrated into design flows to
prevent manufacturing effects from disrupting electrical performance, analyze
systematic and random variability on designs, and optimize designs to maximize
yield.
More information
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Advanced node blog
Statistical Timing Analysis - Has its time arrived?
Tuesday, October 23, 2007
At 45nm chip designs, manufacturing and process control becomes increasingly difficult. Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. STA compensates for this variability by requiring aggressive guard bands and by using multiple corners or scenarios to reflect different manufacturing conditions.
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Double Patterning Lithography and how it requires a paradigm shift in EDA and design
Friday, October 19, 2007
We find ourselves in this intriguing situation where EDA now needs to enable the manufacturing world to remain on Moore's Law. The semiconductor industry has used Moore's law as a synchronization method of ensuring that manufacturing infrastructure is in place to support new designs consistent with the market place and IC suppliers requirements. In the past, manufacturing infrastructure advances took place mostly independently from design. Lithography is the area where this was most true arguably. A simple, and simplistic, example of that is the increasing NA ...
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New blog for advanced node design
Thursday, October 18, 2007
As the size of transistors and other components reaches 65 nanometers and below, chip designers are coming up against some hard realities in design for manufacturability, timing and power.
This blog for advanced node is an open discussion on how to streamline the development of high-performance, manufacturable designs at nanometer geometries. Discussions will center around topics about model-based design, manufacturability, low power and sign-off...
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Thank you for your interest in the Cadence® Low-Power Solution. A Cadence representative will get back to you within two business days.
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By Rahul Deokar | 